Liquid crystal display devices are configured by holding a liquid crystal display element between a pair of glass substrates or the like. The liquid crystal display devices are indispensable for daily life and business, such as car navigation systems, electronic books, digital photo frames, industrial equipment, televisions, personal computers, smartphones, tablet terminals, or the like, by taking advantages of a low profile, lightweight, and low power consumption. In these applications, various modes of liquid crystal display devices relating to an electrode arrangement or a substrate design for changing optical characteristics of the liquid crystal layer are studied.
Display schemes of liquid crystal display devices in recent years include a Vertical Alignment (VA) mode such as a Multi-domain Vertical Alignment (MVA) mode or the like, in which liquid crystal molecules having negative anisotropy of dielectric constant are vertically aligned with respect to the substrate surface, an In-Plane Switching (IPS) mode, in which liquid crystal molecules having positive or negative anisotropy of dielectric constant are horizontally aligned with respect to the substrate surface to apply a transverse electric field to the liquid crystal layer, a Fringe Field Switching (FFS) mode, and the like.
In particular, the FFS mode is a liquid crystal mode frequently used in recent years for smartphones and tablet terminals. As an FFS-mode liquid crystal display device, for example, an FFS-mode liquid crystal display device is disclosed including: a first transparent insulating substrate and a second transparent insulating substrate arranged opposite to each other with a predetermined distance, with a liquid crystal layer including a plurality of liquid crystal molecules interposed between the first and second transparent insulating substrates; a plurality of gate bus lines and data bus lines formed on the first transparent insulating substrate and arranged in a matrix form to define a unit pixel; a thin film transistor formed at an intersection of the gate bus line and the data bus line; a counter electrode disposed in each unit pixel and made of a transparent conductor; and a pixel electrode, made of a transparent conductor, arranged in each unit pixel to generate a fringe field together with the counter electrode, insulated from the counter electrode, and including a plurality of upper slits and a plurality of lower slits symmetrically arranged to each other with respect to a long side of the pixel with a predetermined tilted angle (for example, see PTL 1).